Computer systems such as computer workstations operate due to the passage of information between at least one microprocessor and various subsystems. Communications between the microprocessor(s) and subsystems occur over a data communication pathway called a bus. In a typical multi-processor system, a plurality of processors share common main memory through a bus and a memory controller, with each processor associated with at least one cache and cache controller. In a symmetric multi-processing system (SMP), the plurality of processor elements are coupled together by a processor bus. This processor bus, commonly called the SMP bus, supports a shared memory style of programming. In such computer systems, it is common for one or more processors to access a memory, referred to as a "shared memory." The shared memory may be a memory array that contains a number of memory modules. Access to the shared memory is generally over a shared memory bus. This shared main memory may include synchronous dynamic random access memories (SDRAM). Such systems also include, in many cases, cache memory systems, where a small amount of very fast, expensive static random access memory (SRAM) is used to store copies of data.
In an effort to reduce overall development expenses and design redundancies, there has been a move in the chip design industry to define commonality into chip design development organization across brand name platforms. Part of this work has involved an effort to define a memory controller design that can support, modification, without processors utilizing either sequential burst ordering or interleaved burst ordering. This presents unique challenges to the memory controllers in order to support the different burst ordering that each processor delivers on multi-beat transfers.
In a cache memory system, each time a memory command and address are sent out, the requested information is checked to see if it is contained in a cache memory of one of the system processors. If the data is found, that processor must be given access to the shared bus which links the processors, and links the processors to the memory controller. When this access is given, it will prevent other read commands from being sent out on that bus. For systems with in-line cache controllers, the in-line cache controller that connects each processor to the SMP bus provides a level of cache between the processor and the memory controller, and also delivers a common SMP shared bus to the memory controller. Although the bus protocol among different types of processors is made common by the intermediate cache controller, the data ordering during burst transfers must be addressed by the memory controller design. It should be noted that, although the preferred embodiment includes an in-line cache controller 12, to convert the internal processor bus (not shown) to the SMP bus 14, an alternative embodiment does not include such a controller but provides, instead, for the processor 10 to attach directly to the SMP bus 14.
Some processors support a type of multi-beat burst transfer protocol called "sequential" while others support a multi-beat burst protocol called "interleaved." In a multi-processor system that can support either type of transfer processors, the memory controller must be able to support both sequential and interleaved burst protocols.
Most activities in any system, which include shared memory systems, require one or more clock cycles to complete. Typically, activities take more than one cycle and the required number of cycles vary depending on the dynamic conditions. If the SMP data bus is a quadword in width, then a burst transfer of four beats is needed to support the transfer of a 64-byte cache line (CL), where 1 byte=8 bits, 1 word=4 bytes, and 1 quadword=4 words=16 bytes.
Regarding memory, the SDRAM supports four-beat burst transfers, and can be programmed to operate in either sequential or interleaved burst mode at power-up or reset. This provides a common data burst protocol for processor reads and writes to memory. However, SDRAM features do not address the issue of I/O devices that communicate with the processor or perform direct memory access (DMA) to memory.
In addition to the SMP bus described above, the memory controller in a multi-processor system must also provide support to the IO bus. In a present-day system, there is often a need for input/output (I/O) subsystems, such as monitors, graphics adapters, and IDE-type devices, to receive or send information, via an IO bus to or from a microprocessor. The "interleaved" burst protocol poses a problem for the memory controller as it relates to the 10 bus. The IO bus only supports sequential burst ordering protocol. Therefore, the memory controller must perform an order translation between interleaved and sequential burst ordering where an interleaved-type processor accesses or sends I/O data. The current invention's translation capability between interleaved and sequential burst ordering overcomes the prior art by allowing a memory controller design that can support either sequential and interleaved burst protocols, thus providing commonality heretofore absent in the prior art memory controller systems.